21:15
AutumNeverReturn
module af6cii_enc_hshift8 (
);
parameter STS3C_ID = 4;
wire [31:0] ppcfg_sts3c;
wire [5:0]chid1;
reg [5:0]chid_cv;
always @(ppcfg_sts3c or chid1)//@clk1
begin
case (chid1[STS3C_ID-1:0])
4'd0 : chid_cv = ppcfg_sts3c[0] ? chid1[STS3C_ID-1:0] : chid1;
4'd1 : chid_cv = ppcfg_sts3c[1] ? chid1[STS3C_ID-1:0] : chid1;
4'd2 : chid_cv = ppcfg_sts3c[2] ? chid1[STS3C_ID-1:0] : chid1;
4'd3 : chid_cv = ppcfg_sts3c[3] ? chid1[STS3C_ID-1:0] : chid1;
4'd4 : chid_cv = ppcfg_sts3c[4] ? chid1[STS3C_ID-1:0] : chid1;
4'd5 : chid_cv = ppcfg_sts3c[5] ? chid1[STS3C_ID-1:0] : chid1;
4'd6 : chid_cv = ppcfg_sts3c[6] ? chid1[STS3C_ID-1:0] : chid1;
4'd7 : chid_cv = ppcfg_sts3c[7] ? chid1[STS3C_ID-1:0] : chid1;
4'd8 : chid_cv = ppcfg_sts3c[8] ? chid1[STS3C_ID-1:0] : chid1;
4'd9 : chid_cv = ppcfg_sts3c[9] ? chid1[STS3C_ID-1:0] : chid1;
4'd10: chid_cv = ppcfg_sts3c[10] ? chid1[STS3C_ID-1:0] : chid1;
4'd11: chid_cv = ppcfg_sts3c[11] ? chid1[STS3C_ID-1:0] : chid1;
4'd12: chid_cv = ppcfg_sts3c[12] ? chid1[STS3C_ID-1:0] : chid1;
4'd13 : chid_cv = ppcfg_sts3c[13] ? chid1[STS3C_ID-1:0] : chid1;
4'd14 : chid_cv = ppcfg_sts3c[14] ? chid1[STS3C_ID-1:0] : chid1;
4'd15 : chid_cv = ppcfg_sts3c[15] ? chid1[STS3C_ID-1:0] : chid1;
endcase
end
endmodule
So how can we reduce this complicated! We can use :
generate
begin
end
endgenerate
Let 's see :
module af6cii_enc_hshift8 (
);
parameter STS3C_ID = 4;
wire [31:0] ppcfg_sts3c;
wire [5:0]chid1;
reg [5:0]chid_cv_ary[15:0];
wire [5:0]chid_cv;
assign chid_cv = chid_cv_ary[chid1];
genvar j;
always @(ppcfg_sts3c or chid1)//@clk1
begin
generate for (j = 0;j < 16 ; j = j + 1)
begin : chid_cv_lb
chid_cv_ary[j] = ppcfg_sts3c[j] ? chid1[STS3C_ID-1:0] : chid1;
end
endgenerate
end
endmodule
And there 're many ways to implement this one! If you 're interesting! Pls comment below!
Have fun!
Have fun!
